mirror of
https://github.com/jie65535/stm32f10x-uC-OS-II.git
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116 lines
5.1 KiB
C
116 lines
5.1 KiB
C
/*
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*********************************************************************************************************
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* uC/OS-II
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* The Real-Time Kernel
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*
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*
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* (c) Copyright 2006, Micrium, Weston, FL
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* All Rights Reserved
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*
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* ARM Cortex-M3 Port
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*
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* File : OS_CPU.H
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* Version : V2.86
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* By : Jean J. Labrosse
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* Brian Nagel
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*
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* For : ARMv7M Cortex-M3
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* Mode : Thumb2
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* Toolchain : IAR EWARM
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*********************************************************************************************************
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*/
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#ifndef OS_CPU_H
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#define OS_CPU_H
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#ifdef OS_CPU_GLOBALS
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#define OS_CPU_EXT
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#else
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#define OS_CPU_EXT extern
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#endif
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/*
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*********************************************************************************************************
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* DATA TYPES
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* (Compiler Specific)
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*********************************************************************************************************
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*/
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typedef unsigned char BOOLEAN;
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typedef unsigned char INT8U; /* Unsigned 8 bit quantity */
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typedef signed char INT8S; /* Signed 8 bit quantity */
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typedef unsigned short INT16U; /* Unsigned 16 bit quantity */
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typedef signed short INT16S; /* Signed 16 bit quantity */
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typedef unsigned int INT32U; /* Unsigned 32 bit quantity */
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typedef signed int INT32S; /* Signed 32 bit quantity */
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typedef float FP32; /* Single precision floating point */
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typedef double FP64; /* Double precision floating point */
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typedef unsigned int OS_STK; /* Each stack entry is 32-bit wide */
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typedef unsigned int OS_CPU_SR; /* Define size of CPU status register (PSR = 32 bits) */
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/*
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*********************************************************************************************************
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* Cortex-M1
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* Critical Section Management
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*
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* Method #1: Disable/Enable interrupts using simple instructions. After critical section, interrupts
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* will be enabled even if they were disabled before entering the critical section.
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* NOT IMPLEMENTED
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*
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* Method #2: Disable/Enable interrupts by preserving the state of interrupts. In other words, if
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* interrupts were disabled before entering the critical section, they will be disabled when
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* leaving the critical section.
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* NOT IMPLEMENTED
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*
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* Method #3: Disable/Enable interrupts by preserving the state of interrupts. Generally speaking you
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* would store the state of the interrupt disable flag in the local variable 'cpu_sr' and then
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* disable interrupts. 'cpu_sr' is allocated in all of uC/OS-II's functions that need to
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* disable interrupts. You would restore the interrupt disable state by copying back 'cpu_sr'
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* into the CPU's status register.
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*********************************************************************************************************
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*/
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#define OS_CRITICAL_METHOD 3
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#if OS_CRITICAL_METHOD == 3
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#define OS_ENTER_CRITICAL() {cpu_sr = OS_CPU_SR_Save();}
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#define OS_EXIT_CRITICAL() {OS_CPU_SR_Restore(cpu_sr);}
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#endif
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/*
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*********************************************************************************************************
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* Cortex-M3 Miscellaneous
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*********************************************************************************************************
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*/
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#define OS_STK_GROWTH 1 /* Stack grows from HIGH to LOW memory on ARM */
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#define OS_TASK_SW() OSCtxSw()
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/*
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*********************************************************************************************************
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* PROTOTYPES
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*********************************************************************************************************
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*/
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#if OS_CRITICAL_METHOD == 3 /* See OS_CPU_A.ASM */
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OS_CPU_SR OS_CPU_SR_Save(void);
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void OS_CPU_SR_Restore(OS_CPU_SR cpu_sr);
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#endif
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void OSCtxSw(void);
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void OSIntCtxSw(void);
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void OSStartHighRdy(void);
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void PendSV_Handler(void);
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// /* See OS_CPU_C.C */
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//void OS_CPU_SysTickHandler(void);
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//void OS_CPU_SysTickInit(void);
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/* See BSP.C */
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//INT32U OS_CPU_SysTickClkFreq(void);
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#endif
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